Numbers can be digitally represented using a variety of binary representations, often referred to as number formats. Integer number formats include signed integers, which generally use a two's complement format for representing positive and negative numbers, and unsigned integers, which are restricted to positive values. Floating point or “real” number formats include 16-bit half precision, 32-bit single precision and 64-bit double precision formats, such as those specified in the IEEE 754 series of standards. These formats can include a sign field, an exponent field, and a mantissa or “significand” field for representing a wide range of values.
It is often required to convert a number from one format to another, in order to represent the number in an appropriate format for a particular processing task. Such conversion operations may be required in applications, for example Digital Signal Processing circuits, such as those used in wireless communication applications, as well as other general-purpose or special-purpose computing applications and integrated circuitry. Various applicable conversion circuits such as combinatorial logic circuits are known. However, prior art conversion circuits tend to exhibit performance limitations for example in terms of gate delay, logic depth, power consumption, circuit throughput, number of transistors required for implementation, and the like. In order to improve overall application performance, the performance of number format conversion circuits may require improvement.
Therefore there is a need for a method and apparatus for converting a number from its signed integer representation to its floating point representation, that is not subject to one or more limitations of the prior art.
This background information is provided to reveal information believed by the applicant to be of possible relevance to the present invention. No admission is necessarily intended, nor should be construed, that any of the preceding information constitutes prior art against the present invention.